A low-complexity interleaved image wavelet transform architecture for a visual sensor node

L. M. Ang; L. S. Yeong; K. P. Seng

doi:10.1109/ICCIAS.2006.295365

A low-complexity interleaved image wavelet transform architecture for a visual sensor node

L. M. Ang, L. S. Yeong, K. P. Seng

University of Nottingham

Research output: Book chapter/Published conference paper › Conference paper › peer-review

1 Citation (Scopus)

Abstract

We present a low-complexity architecture to perform a wavelet subband decomposition on an image captured from a visual sensor. The input into the architecture is a dynamic stream of image data from the visual sensor. The subband coefficients are computed on-the-fly as the data flow through the architecture. The output from the architecture is a stream of interleaved subband coefficients. A 160×120 image pixels architecture to perform three scales of subband decomposition has been synthesized and implemented on a Xilinx FPGA utilizing a chip area of 940 Slices.

Original language	English
Title of host publication	2006 International Conference on Computational Intelligence and Security, ICCIAS 2006
Pages	1767-1770
Number of pages	4
Volume	2
DOIs	https://doi.org/10.1109/ICCIAS.2006.295365
Publication status	Published - 01 Dec 2007
Event	2006 International Conference on Computational Intelligence and Security, ICCIAS 2006 - Guangzhou, China Duration: 03 Oct 2006 → 06 Oct 2006

Conference

Conference	2006 International Conference on Computational Intelligence and Security, ICCIAS 2006
Country/Territory	China
City	Guangzhou
Period	03/10/06 → 06/10/06

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10.1109/ICCIAS.2006.295365

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title = "A low-complexity interleaved image wavelet transform architecture for a visual sensor node",

abstract = "We present a low-complexity architecture to perform a wavelet subband decomposition on an image captured from a visual sensor. The input into the architecture is a dynamic stream of image data from the visual sensor. The subband coefficients are computed on-the-fly as the data flow through the architecture. The output from the architecture is a stream of interleaved subband coefficients. A 160×120 image pixels architecture to perform three scales of subband decomposition has been synthesized and implemented on a Xilinx FPGA utilizing a chip area of 940 Slices.",

author = "Ang, {L. M.} and Yeong, {L. S.} and Seng, {K. P.}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/ICCIAS.2006.295365",

language = "English",

isbn = "1424406056",

volume = "2",

pages = "1767--1770",

booktitle = "2006 International Conference on Computational Intelligence and Security, ICCIAS 2006",

note = "2006 International Conference on Computational Intelligence and Security, ICCIAS 2006 ; Conference date: 03-10-2006 Through 06-10-2006",

}

Ang, LM, Yeong, LS & Seng, KP 2007, A low-complexity interleaved image wavelet transform architecture for a visual sensor node. in 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006. vol. 2, 4076271, pp. 1767-1770, 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006, Guangzhou, China, 03/10/06. https://doi.org/10.1109/ICCIAS.2006.295365

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T1 - A low-complexity interleaved image wavelet transform architecture for a visual sensor node

AU - Ang, L. M.

AU - Yeong, L. S.

AU - Seng, K. P.

PY - 2007/12/1

Y1 - 2007/12/1

N2 - We present a low-complexity architecture to perform a wavelet subband decomposition on an image captured from a visual sensor. The input into the architecture is a dynamic stream of image data from the visual sensor. The subband coefficients are computed on-the-fly as the data flow through the architecture. The output from the architecture is a stream of interleaved subband coefficients. A 160×120 image pixels architecture to perform three scales of subband decomposition has been synthesized and implemented on a Xilinx FPGA utilizing a chip area of 940 Slices.

AB - We present a low-complexity architecture to perform a wavelet subband decomposition on an image captured from a visual sensor. The input into the architecture is a dynamic stream of image data from the visual sensor. The subband coefficients are computed on-the-fly as the data flow through the architecture. The output from the architecture is a stream of interleaved subband coefficients. A 160×120 image pixels architecture to perform three scales of subband decomposition has been synthesized and implemented on a Xilinx FPGA utilizing a chip area of 940 Slices.

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U2 - 10.1109/ICCIAS.2006.295365

DO - 10.1109/ICCIAS.2006.295365

M3 - Conference paper

SN - 1424406056

SN - 9781424406050

VL - 2

SP - 1767

EP - 1770

BT - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006

T2 - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006

Y2 - 3 October 2006 through 6 October 2006

ER -

A low-complexity interleaved image wavelet transform architecture for a visual sensor node

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