TY - JOUR
T1 - A residue number system hardware design of fast-search variable-motion-estimation accelerator for HEVC/H.265
AU - Vayalil, Niras C.
AU - Paul, Manoranjan
AU - Kong, Yinan
N1 - Includes bibliographical references.
PY - 2017
Y1 - 2017
N2 - A residue number system (RNS) has an inherent parallel structure that can be utilized for improving computer hardware systems. An RNS represents large integer numbers as a smaller integer set, or residues of a modulo set, without carry propagation between them. Hence mathematical operations such as addition or subtraction can be performed on the residues independently. This paper proposes an RNS implementation of motion estimation for the latest video coding standard known as high-efficiency video coding (HEVC) or H.265. Since motion estimation is the most computationally intensive task in video coding, several simplified algorithms are proposed for mitigating the problem, but the majority of them result in a worsening peak signal-to-noise ratio (PSNR) or bit-rate performance, or sometimes both. This paper also proposes a modified algorithm based on a test-zone (TZ) search algorithm, a widely used fastsearch algorithm with good rate-distortion (RD) performance, suitable for hardware implementation for encoding ultra-highdefinition (UHD) videos in real time. The results show that worstcase PSNR degradation and bit-rate increases compared to the TZ search in the HEVC reference software implementation are negligible, and the hardware gate count is less than for many other designs in the literature.
AB - A residue number system (RNS) has an inherent parallel structure that can be utilized for improving computer hardware systems. An RNS represents large integer numbers as a smaller integer set, or residues of a modulo set, without carry propagation between them. Hence mathematical operations such as addition or subtraction can be performed on the residues independently. This paper proposes an RNS implementation of motion estimation for the latest video coding standard known as high-efficiency video coding (HEVC) or H.265. Since motion estimation is the most computationally intensive task in video coding, several simplified algorithms are proposed for mitigating the problem, but the majority of them result in a worsening peak signal-to-noise ratio (PSNR) or bit-rate performance, or sometimes both. This paper also proposes a modified algorithm based on a test-zone (TZ) search algorithm, a widely used fastsearch algorithm with good rate-distortion (RD) performance, suitable for hardware implementation for encoding ultra-highdefinition (UHD) videos in real time. The results show that worstcase PSNR degradation and bit-rate increases compared to the TZ search in the HEVC reference software implementation are negligible, and the hardware gate count is less than for many other designs in the literature.
KW - High-efficiency video coding (HEVC)
KW - Motion estimation (ME)
KW - Residue number system (RNS)
KW - Very large scale integration (VLSI) architecture
UR - http://www.scopus.com/inward/record.url?scp=85039801657&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85039801657&partnerID=8YFLogxK
U2 - 10.1109/TCSVT.2017.2787194
DO - 10.1109/TCSVT.2017.2787194
M3 - Article
AN - SCOPUS:85039801657
SN - 1051-8215
VL - 29
SP - 572
EP - 581
JO - IEEE Transactions on Circuits and Systems for Video Technology
JF - IEEE Transactions on Circuits and Systems for Video Technology
IS - 2
ER -