A very compact AES-SPIHT selective encryption computer architecture design with improved S-Box

Jia Hao Kong, Li-Minn Ang, Kah Phooi Seng

    Research output: Contribution to journalArticlepeer-review

    6 Citations (Scopus)
    11 Downloads (Pure)

    Abstract

    The "S-box" algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the Sbox circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact cryptoprocessor's application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithmas a complete selective encryption system.
    Original languageEnglish
    Article number785126
    Pages (from-to)1-26
    Number of pages26
    JournalJournal of Engineering
    Volume2013
    DOIs
    Publication statusPublished - 2013

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