Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits

Research output: Book chapter/Published conference paperConference paper

Abstract

In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.
Original languageEnglish
Title of host publication2nd International Conference on Education Technology and Computer (ICETC), 2010
PublisherIEEExplore
Pages134-138
Number of pages5
ISBN (Electronic)9781424463671
DOIs
Publication statusPublished - 2010
EventInternational Conference on Education Technology and Computer (ICETC) - Shanghai, China
Duration: 22 Jun 201024 Jun 2010

Conference

ConferenceInternational Conference on Education Technology and Computer (ICETC)
CountryChina
Period22/06/1024/06/10

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  • Cite this

    Penatiyana Withanage, C., Beg, A. H., & Singh, A. (2010). Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits. In 2nd International Conference on Education Technology and Computer (ICETC), 2010 (pp. 134-138). IEEExplore. https://doi.org/10.1109/ICETC.2010.5529799