Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits

Chandana Penatiyana Withanage; Abul Hashem Beg; A Singh

doi:10.1109/ICETC.2010.5529799

Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits

Chandana Penatiyana Withanage, Abul Hashem Beg, A Singh

Research output: Book chapter/Published conference paper › Conference paper › peer-review

Abstract

In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

Original language	English
Title of host publication	2nd International Conference on Education Technology and Computer (ICETC), 2010
Publisher	IEEExplore
Pages	134-138
Number of pages	5
ISBN (Electronic)	9781424463671
DOIs	https://doi.org/10.1109/ICETC.2010.5529799
Publication status	Published - 2010
Event	International Conference on Education Technology and Computer (ICETC) - Shanghai, China Duration: 22 Jun 2010 → 24 Jun 2010

Conference

Conference	International Conference on Education Technology and Computer (ICETC)
Country/Territory	China
Period	22/06/10 → 24/06/10

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10.1109/ICETC.2010.5529799

Cite this

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title = "Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits",

abstract = "In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.",

author = "{Penatiyana Withanage}, Chandana and Beg, {Abul Hashem} and A Singh",

note = "Imported on 03 May 2017 - DigiTool details were: publisher = IEEExplore, 2010. Event dates (773o) = 22-06-2010-24-06-2010; Parent title (773t) = International Conference on Education Technology and Computer (ICETC).; International Conference on Education Technology and Computer (ICETC) ; Conference date: 22-06-2010 Through 24-06-2010",

year = "2010",

doi = "10.1109/ICETC.2010.5529799",

language = "English",

pages = "134--138",

booktitle = "2nd International Conference on Education Technology and Computer (ICETC), 2010",

publisher = "IEEExplore",

}

Penatiyana Withanage, C, Beg, AH & Singh, A 2010, Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits. in 2nd International Conference on Education Technology and Computer (ICETC), 2010. IEEExplore, pp. 134-138, International Conference on Education Technology and Computer (ICETC), China, 22/06/10. https://doi.org/10.1109/ICETC.2010.5529799

Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits. / Penatiyana Withanage, Chandana; Beg, Abul Hashem; Singh, A.
2nd International Conference on Education Technology and Computer (ICETC), 2010. IEEExplore, 2010. p. 134-138.

Research output: Book chapter/Published conference paper › Conference paper › peer-review

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AU - Penatiyana Withanage, Chandana

AU - Beg, Abul Hashem

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N1 - Imported on 03 May 2017 - DigiTool details were: publisher = IEEExplore, 2010. Event dates (773o) = 22-06-2010-24-06-2010; Parent title (773t) = International Conference on Education Technology and Computer (ICETC).

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N2 - In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

AB - In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

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DO - 10.1109/ICETC.2010.5529799

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BT - 2nd International Conference on Education Technology and Computer (ICETC), 2010

PB - IEEExplore

T2 - International Conference on Education Technology and Computer (ICETC)

Y2 - 22 June 2010 through 24 June 2010

ER -

Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-variable Circuits

Abstract

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