Dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing

Li minn Ang, Hon Nin Cheung, Kamran Eshraghian

    Research output: Book chapter/Published conference paperConference paperpeer-review

    10 Citations (Scopus)

    Abstract

    In this paper, we present a dataflow-oriented architecture for a modified SPIHT algorithm which is suitable for VLSI implementation. The input into the architecture is a bit stream of the wavelet coefficients in the depth-first search (DFS) format and the output from the architecture is a data stream containing the significance map (MAP) and successive-approximation quantization (SAQ) symbols for the SPIHT algorithm. The memory requirements for the architecture are reduced by transmitting the MAP and SAQ symbols as they are generated. The MAP and SAQ symbols are formulated in view of the DFS coefficient bit stream and the corresponding VLSI architecture to implement the formulated requirements is presented. Simulations are also presented to compare the coding efficiency for the modified SPIHT architecture versus the complete SPIHT algorithm.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Volume1
    Publication statusPublished - 03 Dec 2000
    EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
    Duration: 28 May 200031 May 2000

    Publication series

    NameProceedings - IEEE International Symposium on Circuits and Systems
    ISSN (Print)0271-4310

    Conference

    ConferenceProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems
    CityGeneva, Switz
    Period28/05/0031/05/00

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