FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection

Tirath Ramdas, Li Minn Ang, Greg Egan

    Research output: Book chapter/Published conference paperConference paperpeer-review

    9 Citations (Scopus)

    Abstract

    We present an FPGA implementation of an integer-based MIPS processor using the Handel-C hardware design language (HDL). The processor is implemented on the RC200 development board from Celoxica. The processor implementation is modified from the standard MIPS architecture to lake into account the limitations and features of the board. A face detection system is implemented with the processor to show its application towards real-time image processing.

    Original languageEnglish
    Title of host publicationProceedings of the IEEE Region 10 Annual International Conference/TENCON
    Publication statusPublished - 01 Dec 2004
    EventIEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand
    Duration: 21 Nov 200424 Nov 2004

    Conference

    ConferenceIEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering
    Country/TerritoryThailand
    CityChiang Mai
    Period21/11/0424/11/04

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