Hardware implementation of the depth first search bit stream SPIHT system

Li Minn Ang, Hon Nin Cheung

    Research output: Book chapter/Published conference paperConference paperpeer-review

    4 Citations (Scopus)

    Abstract

    In this paper, we present a hardware implementation of an embedded wavelet coding system using the Set Partitioning in Hierarchical Trees (SPIHT) algorithm. The coding system can be switched to perform encoding and decoding on the same device. The input into the system during encoding is a stream of image pixels and the output is an encoded bit stream ready for transmission. The system produces the reconstructed image data from the received bit stream during decoding. The coding system consists of discrete wavelet transform (DWT) and IDWT modules and tree searching quantization (TS) and ITS modules. It uses two memory banks for processing: coefficient memory bank and subtree memory bank. To reduce storage requirements, the coefficient memory bank is used at different stages of processing to store the image pixels or wavelet coefficients. In the encoding stage, the coefficient memory bank contains the image pixels initially. After the DWT is performed, the memory bank contains the wavelet coefficients. During decoding, the coefficient memory bank stores the reconstructed coefficients and after the IDWT contains the decoded image pixels.

    Original languageEnglish
    Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
    Pages518-521
    Number of pages4
    Volume4
    DOIs
    Publication statusPublished - 01 Dec 2001
    Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
    Duration: 06 May 200109 May 2001

    Conference

    Conference2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
    Country/TerritoryAustralia
    CitySydney, NSW
    Period06/05/0109/05/01

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