Implementation of (15, 9) Reed Solomon Minimal Instruction set computing on FPGA using handel-C

Jia Jan Ong, L. M. Ang, K. P. Seng

    Research output: Book chapter/Published conference paperConference paperpeer-review

    1 Citation (Scopus)

    Abstract

    Reed Solomon coding has an important role to play as to sustain reliability of data communication. However, the encoder consumes significant amount of power that affects the cost of producing the hardware. Besides, the complicated encoder circuit also does affect the cost of implemented hardware. There is a need to build a simple encoder which does the similar data encoding function. By amalgamate One Instruction Set Computer (OISC) and the Galois Field arithmetic, a Reed Solomon Minimal Instruction Computer (MISC) processor is developed. This processor has simpler circuit that still has the same encoded codeword produced.

    Original languageEnglish
    Title of host publicationICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics
    Pages356-361
    Number of pages6
    DOIs
    Publication statusPublished - 01 Dec 2010
    Event2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010 - Kuala Lumpur, Malaysia
    Duration: 05 Dec 201007 Dec 2010

    Conference

    Conference2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010
    Country/TerritoryMalaysia
    CityKuala Lumpur
    Period05/12/1007/12/10

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