Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

J.H. Kong; L.-M. Ang; K.P. Seng; F.T. Ong

doi:10.1109/ICOIN.2011.5723161

Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

J.H. Kong, L.-M. Ang, K.P. Seng, F.T. Ong

University of Nottingham

Research output: Book chapter/Published conference paper › Conference paper › peer-review

3 Citations (Scopus)

Abstract

This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. ©2011 IEEE.

Original language	English
Title of host publication	Proceedings of the 25th International Conference on Information Networking (ICOIN 2011)
Place of Publication	USA
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	472-477
DOIs	https://doi.org/10.1109/ICOIN.2011.5723161
Publication status	Published - 2011
Event	2011 International Conference on Information Networking (ICOIN) - Sunway Lagoon Resort Hotel, Kuala Lumpur, Malaysia Duration: 26 Jan 2011 → 28 Jan 2011

Conference

Conference	2011 International Conference on Information Networking (ICOIN)
Country/Territory	Malaysia
City	Kuala Lumpur
Period	26/01/11 → 28/01/11
Other	This is the 25th Edition of the International Conference on Information Networking (ICOIN), which was started under the name of Joint Workshop on Computer Communication in 1986. ICOIN 2011 will take place in Kuala Lumpur, Malaysia. The conference is organized by Korea Institute of Information Scientists and Engineers (KIISE), Korea. The ICOIN 2011 conference looks for significant contributions to the computer communications, wireless networks and converged networks in the theoretical and practical aspects.

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https://www.scopus.com/inward/record.uri?eid=2-s2.0-79952936896&doi=10.1109%2fICOIN.2011.5723161&partnerID=40&md5=ae386729c54d07e3ebe13ddc072ff66b

Cite this

@inproceedings{3674792ad24b4b4e83b5fd6193d6c1f5,

title = "Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption",

abstract = "This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. {\textcopyright}2011 IEEE.",

author = "J.H. Kong and L.-M. Ang and K.P. Seng and F.T. Ong",

year = "2011",

doi = "10.1109/ICOIN.2011.5723161",

language = "English",

pages = "472--477",

booktitle = "Proceedings of the 25th International Conference on Information Networking (ICOIN 2011)",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2011 International Conference on Information Networking (ICOIN) ; Conference date: 26-01-2011 Through 28-01-2011",

}

Kong, JH, Ang, L-M, Seng, KP & Ong, FT 2011, Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. in Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). IEEE, Institute of Electrical and Electronics Engineers, USA, pp. 472-477, 2011 International Conference on Information Networking (ICOIN), Kuala Lumpur, Malaysia, 26/01/11. https://doi.org/10.1109/ICOIN.2011.5723161

Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. / Kong, J.H.; Ang, L.-M.; Seng, K.P. et al.
Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). USA: IEEE, Institute of Electrical and Electronics Engineers, 2011. p. 472-477.

Research output: Book chapter/Published conference paper › Conference paper › peer-review

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T1 - Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

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AU - Ang, L.-M.

AU - Seng, K.P.

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Y1 - 2011

N2 - This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. ©2011 IEEE.

AB - This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. ©2011 IEEE.

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DO - 10.1109/ICOIN.2011.5723161

M3 - Conference paper

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BT - Proceedings of the 25th International Conference on Information Networking (ICOIN 2011)

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - USA

T2 - 2011 International Conference on Information Networking (ICOIN)

Y2 - 26 January 2011 through 28 January 2011

ER -

Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

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