Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption

J.H. Kong, L.-M. Ang, K.P. Seng, F.T. Ong

Research output: Book chapter/Published conference paperConference paper

3 Citations (Scopus)

Abstract

This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. ©2011 IEEE.
Original languageEnglish
Title of host publicationProceedings of the 25th International Conference on Information Networking (ICOIN 2011)
Place of PublicationUSA
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages472-477
DOIs
Publication statusPublished - 2011
Event2011 International Conference on Information Networking (ICOIN) - Sunway Lagoon Resort Hotel, Kuala Lumpur, Malaysia
Duration: 26 Jan 201128 Jan 2011

Conference

Conference2011 International Conference on Information Networking (ICOIN)
CountryMalaysia
CityKuala Lumpur
Period26/01/1128/01/11
OtherThis is the 25th Edition of the International Conference on Information Networking (ICOIN), which was started under the name of Joint Workshop on Computer Communication in 1986. ICOIN 2011 will take place in Kuala Lumpur, Malaysia. The conference is organized by Korea Institute of Information Scientists and Engineers (KIISE), Korea. The ICOIN 2011 conference looks for significant contributions to the computer communications, wireless networks and converged networks in the theoretical and practical aspects.

Fingerprint

Computer architecture
Computer hardware
Sensor networks
Cryptography
Computer hardware description languages
Adders
Random access storage
Field programmable gate arrays (FPGA)
Data storage equipment

Cite this

Kong, J. H., Ang, L-M., Seng, K. P., & Ong, F. T. (2011). Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. In Proceedings of the 25th International Conference on Information Networking (ICOIN 2011) (pp. 472-477). USA: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICOIN.2011.5723161
Kong, J.H. ; Ang, L.-M. ; Seng, K.P. ; Ong, F.T. / Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). USA : IEEE, Institute of Electrical and Electronics Engineers, 2011. pp. 472-477
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title = "Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption",
abstract = "This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1{\%} of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. {\circledC}2011 IEEE.",
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Kong, JH, Ang, L-M, Seng, KP & Ong, FT 2011, Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. in Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). IEEE, Institute of Electrical and Electronics Engineers, USA, pp. 472-477, 2011 International Conference on Information Networking (ICOIN), Kuala Lumpur, Malaysia, 26/01/11. https://doi.org/10.1109/ICOIN.2011.5723161

Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. / Kong, J.H.; Ang, L.-M.; Seng, K.P.; Ong, F.T.

Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). USA : IEEE, Institute of Electrical and Electronics Engineers, 2011. p. 472-477.

Research output: Book chapter/Published conference paperConference paper

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AB - This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce. ©2011 IEEE.

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Kong JH, Ang L-M, Seng KP, Ong FT. Low-complexity two instruction set computer architecture for sensor network using Skipjack encryption. In Proceedings of the 25th International Conference on Information Networking (ICOIN 2011). USA: IEEE, Institute of Electrical and Electronics Engineers. 2011. p. 472-477 https://doi.org/10.1109/ICOIN.2011.5723161