Minimal instruction set AES processor using Harvard architecture

J. H. Kong; L. M. Ang; K. P. Seng

doi:10.1109/ICCSIT.2010.5564522

Minimal instruction set AES processor using Harvard architecture

J. H. Kong, L. M. Ang, K. P. Seng

Research output: Book chapter/Published conference paper › Conference paper › peer-review

2 Citations (Scopus)

Abstract

This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

Original language	English
Title of host publication	Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Pages	65-69
Number of pages	5
Volume	9
DOIs	https://doi.org/10.1109/ICCSIT.2010.5564522
Publication status	Published - 01 Nov 2010
Event	2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 - Chengdu, China Duration: 09 Jul 2010 → 11 Jul 2010

Conference

Conference	2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Country	China
City	Chengdu
Period	09/07/10 → 11/07/10

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10.1109/ICCSIT.2010.5564522

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abstract = "This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.",

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Kong, JH, Ang, LM & Seng, KP 2010, Minimal instruction set AES processor using Harvard architecture. in Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010. vol. 9, 5564522, pp. 65-69, 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, Chengdu, China, 09/07/10. https://doi.org/10.1109/ICCSIT.2010.5564522

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AB - This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

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Minimal instruction set AES processor using Harvard architecture

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