Minimal instruction set AES processor using Harvard architecture

J. H. Kong, L. M. Ang, K. P. Seng

    Research output: Book chapter/Published conference paperConference paperpeer-review

    4 Citations (Scopus)

    Abstract

    This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

    Original languageEnglish
    Title of host publicationProceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
    Pages65-69
    Number of pages5
    Volume9
    DOIs
    Publication statusPublished - 01 Nov 2010
    Event2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 - Chengdu, China
    Duration: 09 Jul 201011 Jul 2010

    Conference

    Conference2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
    Country/TerritoryChina
    CityChengdu
    Period09/07/1011/07/10

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