Minimal Instruction Set FPGA AES processor using Handel - C

J. H. Kong; L. M. Ang; K. P. Seng; Achonu Oluwole Adejo

doi:10.1109/ICCAIE.2010.5735100

Minimal Instruction Set FPGA AES processor using Handel - C

J. H. Kong, L. M. Ang, K. P. Seng, Achonu Oluwole Adejo

Research output: Book chapter/Published conference paper › Conference paper › peer-review

2 Citations (Scopus)

Abstract

This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.

Original language	English
Title of host publication	ICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics
Pages	340-344
Number of pages	5
DOIs	https://doi.org/10.1109/ICCAIE.2010.5735100
Publication status	Published - 01 Dec 2010
Event	2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010 - Kuala Lumpur, Malaysia Duration: 05 Dec 2010 → 07 Dec 2010

Conference

Conference	2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	05/12/10 → 07/12/10

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICCAIE.2010.5735100

Cite this

@inproceedings{568ce5d104fb4110aac9885eae848e89,

title = "Minimal Instruction Set FPGA AES processor using Handel - C",

abstract = "This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.",

keywords = "AES, Minimal Instruction Set Computer",

author = "Kong, {J. H.} and Ang, {L. M.} and Seng, {K. P.} and Adejo, {Achonu Oluwole}",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ICCAIE.2010.5735100",

language = "English",

isbn = "9781424490554",

pages = "340--344",

booktitle = "ICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics",

note = "2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010 ; Conference date: 05-12-2010 Through 07-12-2010",

}

Kong, JH, Ang, LM, Seng, KP & Adejo, AO 2010, Minimal Instruction Set FPGA AES processor using Handel - C. in ICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics., 5735100, pp. 340-344, 2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010, Kuala Lumpur, Malaysia, 05/12/10. https://doi.org/10.1109/ICCAIE.2010.5735100

TY - GEN

T1 - Minimal Instruction Set FPGA AES processor using Handel - C

AU - Kong, J. H.

AU - Ang, L. M.

AU - Seng, K. P.

AU - Adejo, Achonu Oluwole

PY - 2010/12/1

Y1 - 2010/12/1

N2 - This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.

AB - This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.

KW - AES

KW - Minimal Instruction Set Computer

UR - http://www.scopus.com/inward/record.url?scp=79953867288&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79953867288&partnerID=8YFLogxK

U2 - 10.1109/ICCAIE.2010.5735100

DO - 10.1109/ICCAIE.2010.5735100

M3 - Conference paper

AN - SCOPUS:79953867288

SN - 9781424490554

SP - 340

EP - 344

BT - ICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics

T2 - 2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010

Y2 - 5 December 2010 through 7 December 2010

ER -

Minimal Instruction Set FPGA AES processor using Handel - C

Abstract

Conference

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this