Minimal Instruction Set FPGA AES processor using Handel - C

J. H. Kong, L. M. Ang, K. P. Seng, Achonu Oluwole Adejo

    Research output: Book chapter/Published conference paperConference paperpeer-review

    2 Citations (Scopus)

    Abstract

    This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.

    Original languageEnglish
    Title of host publicationICCAIE 2010 - 2010 International Conference on Computer Applications and Industrial Electronics
    Pages340-344
    Number of pages5
    DOIs
    Publication statusPublished - 01 Dec 2010
    Event2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010 - Kuala Lumpur, Malaysia
    Duration: 05 Dec 201007 Dec 2010

    Conference

    Conference2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010
    Country/TerritoryMalaysia
    CityKuala Lumpur
    Period05/12/1007/12/10

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