Parallel architecture for the implementation of the embedded zerotree wavelet algorithm

Hon Nin Cheung, Li Minn Ang, K. Eshraghian

Research output: Book chapter/Published conference paperConference paper

2 Citations (Scopus)

Abstract

We propose a parallel architecture for the implementation of the embedded zerotree wavelet (EZW) algorithm, based on the depth-first search (DFS) bit stream (BS) architecture. Using the depth-first search of the wavelet coefficient tree, the wavelet coefficients in the coefficient tree are first partitioned into independent sub-trees. In the case of full parallelism, each of the sub-trees is processed by an independent processor. The output from each processor is then multiplexed back into a single output bit stream. While the output bit stream from each sub-tree processor is in the depth-first search format, the overall multiplexed output bit stream represents the search of the sub-trees in parallel. The implementation of each of the sub-tree EZW processor is based on the DFS BS architecture, which accepts the bits of the coefficients in decreasing order of significance from a sub-tree. All the bits in a significant bit plane are processed to produce the output bit stream from the architecture in one scan of the sub-trees. The rise of the DFS BS structure also makes it possible for partial parallelism where a sub-tree processor can process two or more sub-trees in sequence. This provides flexibility for the design of the overall processor optimally to match the speed of the overall input bit stream. The emphasis in this paper is on the parallel processing aspect of the DFS BS architecture. A sub-tree processor can be easily modified to perform any improved EZW algorithm, and the multiplexer for the output bit streams from the processors can be modified to produce the format of the EZW algorithm based on other tree searching schemes similar to the SPIHT algorithm.

Original languageEnglish
Title of host publicationProceedings - 5th Australasian Computer Architecture Conference, ACAC 2000
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages3-8
Number of pages6
ISBN (Electronic)0769505120, 9780769505121
DOIs
Publication statusPublished - 01 Jan 2000
Event5th Australasian Computer Architecture Conference, ACAC 2000 - Canberra, Australia
Duration: 31 Jan 200003 Feb 2000

Conference

Conference5th Australasian Computer Architecture Conference, ACAC 2000
CountryAustralia
CityCanberra
Period31/01/0003/02/00

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  • Cite this

    Cheung, H. N., Ang, L. M., & Eshraghian, K. (2000). Parallel architecture for the implementation of the embedded zerotree wavelet algorithm. In Proceedings - 5th Australasian Computer Architecture Conference, ACAC 2000 (pp. 3-8). [824316] IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ACAC.2000.824316