Smart pixel VLSI architecture for embedded zerotree wavelet coding

Hon Nin Cheung, Geoff Alagoda, Kamran Eshragian, Li Minn Ang

Research output: Book chapter/Published conference paperConference paper

1 Citation (Scopus)

Abstract

The smart pixel (SP) architecture is an array processor architecture which combines image capture and processing on a single device. Previously, an architecture to perform the discrete wavelet transform (DWT) within the SP array has been reported. A feature of the SP-DWT architecture is that the wavelet coefficients for each subband are not clustered together but are distributed in a certain pattern throughout the SP array. An encoder architecture for the embedded zerotree wavelet (EZW) algorithm has been reported which makes use of a modified EZW algorithm where instead of having to scan the whole wavelet coefficient in each pass of the algorithm, the modified algorithm only requires the scanning of one bit of the coefficient in each pass. In this paper, we present a scheme which takes advantage of the coefficient distribution in the SP array so that the bits of the coefficients are shifted out of the SP array in such a way that they can be input into the EZW encoder immediately with minimum buffering requirements.

Original languageEnglish
Title of host publicationISSPA 1999 - Proceedings of the 5th International Symposium on Signal Processing and Its Applications
PublisherIEEE Computer Society
Pages693-696
Number of pages4
Volume2
ISBN (Print)1864354518, 9781864354515
DOIs
Publication statusPublished - 01 Jan 1999
Event5th International Symposium on Signal Processing and Its Applications, ISSPA 1999 - Brisbane, QLD, Australia
Duration: 22 Aug 199925 Aug 1999

Conference

Conference5th International Symposium on Signal Processing and Its Applications, ISSPA 1999
CountryAustralia
CityBrisbane, QLD
Period22/08/9925/08/99

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