VLSI architecture for significance map coding of embedded zerotree wavelet coefficients

Li minn Ang, Hon Nin Cheung, Kamran Eshraghian

Research output: Book chapter/Published conference paperConference paperpeer-review

5 Citations (Scopus)

Abstract

In this paper, we present a hardware architecture to implement the significance map coding for the embedded zerotree wavelet (EZW) algorithm. The architecture is regular and modular and is suitable for VLSI implementation. The approach is based on developing an efficient scheme to determine ancestor-descendant relationships in the wavelet coefficient data stream by rearrangement of the data stream for simpler VLSI implementation. The significance map coding for the EZW algorithm is formulated in view of the rearranged data stream and the corresponding VLSI architecture to implement the formulated requirements is presented.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
Pages627-630
Number of pages4
Publication statusPublished - 01 Dec 1998
EventProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) - Chiangmai, Thailand
Duration: 24 Nov 199827 Nov 1998

Conference

ConferenceProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98)
CityChiangmai, Thailand
Period24/11/9827/11/98

Fingerprint

Dive into the research topics of 'VLSI architecture for significance map coding of embedded zerotree wavelet coefficients'. Together they form a unique fingerprint.

Cite this