VLSI decoder architecture for embedded zerotree wavelet algorithm

Li minn Ang, Hon Nin Cheung, Kamran Eshraghian

Research output: Book chapter/Published conference paperConference paper

4 Citations (Scopus)

Abstract

In this paper, we present a hardware architecture to implement the decoder for the embedded zerotree wavelet (EZW) algorithm. The decoder architecture complements an encoder architecture for the EZW algorithm which has been reported recently. Similar to the reported encoder architecture, the proposed decoder architecture is regular and modular and is suitable for VLSI implementation. The input into the decoder architecture is the output data stream from the encoder architecture containing the significance map symbols and the successive-approximation quantization symbols of the EZW algorithm. The decoding for the EZW algorithm is formulated in view of the output data stream from the encoder and the corresponding VLSI architecture to implement the formulated requirements is presented. The proposed EZW decoder architecture together with the encoder architecture forms a basis for a scalable image or video coding system which is suitable for ASIC VLSI implementation.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 01 Jan 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: 30 May 199902 Jun 1999

Conference

ConferenceProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period30/05/9902/06/99

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  • Cite this

    Ang, L. M., Cheung, H. N., & Eshraghian, K. (1999). VLSI decoder architecture for embedded zerotree wavelet algorithm. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1)